Question # 1 of 10 ( Start time: 03:40:29 PM ) Total Marks: 1
Design of state diagram is one of many steps used to design
Select correct option:
a clock
a truncated counter
an UP/DOWN counter
any counter
Design of state diagram is one of many steps used to design
Select correct option:
a clock
a truncated counter
an UP/DOWN counter
any counter
Question # 2 of 10 ( Start time: 03:40:29 PM ) Total Marks: 1
An Astable multivibrator is known as a(n) _____
Select correct option:
Oscillator
Booster
One-shot
Dual-shot
An Astable multivibrator is known as a(n) _____
Select correct option:
Oscillator
Booster
One-shot
Dual-shot
Question # 3 of 10 ( Start time: 03:40:29 PM ) Total Marks: 1
The glitches due to "Race Condition" can be avoided by using a _________
Select correct option:
Gated flip-flops
Pulse triggered flip-flops
Positive-Edge triggered flip-flops
Negative-Edge triggered flip-flops
Question # 4 of 10 ( Start time: 03:40:29 PM ) Total Marks: 1
A decade counter is ________
Select correct option:
Mod-3 counter
Mod-5 counter
Mod-8 counter
Mod-10 counter
A decade counter is ________
Select correct option:
Mod-3 counter
Mod-5 counter
Mod-8 counter
Mod-10 counter
Question # 5 of 10 ( Start time: 03:40:29 PM ) Total Marks: 1
The terminal count of a 4-bit binary counter in the DOWN mode is__________
Select correct option:
0000
0011
1100
1111
The terminal count of a 4-bit binary counter in the DOWN mode is__________
Select correct option:
0000
0011
1100
1111
Question # 6 of 10 ( Start time: 03:40:50 PM ) Total Marks: 1
The Synchronous counters are also known as Ripple Counters:
Select correct option:
True
False
The Synchronous counters are also known as Ripple Counters:
Select correct option:
True
False
Question # 7 of 10 ( Start time: 03:41:08 PM ) Total Marks: 1
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
Select correct option:
Race condition
Clock Skew
Ripple Effect
None of given options
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
Select correct option:
Race condition
Clock Skew
Ripple Effect
None of given options
Question # 8 of 10 ( Start time: 03:41:27 PM ) Total Marks: 1
Divide-by-160 counter is acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Divide-by-160 counter is acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Question # 9 of 10 ( Start time: 03:41:44 PM ) Total Marks: 1
Design of state diagram is one of many steps used to design
Select correct option:
a clock
a truncated counter
an UP/DOWN counter
any counter
Design of state diagram is one of many steps used to design
Select correct option:
a clock
a truncated counter
an UP/DOWN counter
any counter
Question # 10 of 10 ( Start time: 03:42:01 PM ) Total Marks: 1
In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is__________
Select correct option:
0000
1111
0001
10000
In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is__________
Select correct option:
0000
1111
0001
10000
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