Question # 1 of 10 ( Start
time: 03:03:55 PM ) Total Marks: 1
Divide-by-32 counter can be acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
Flip-Flop and DIV 32
DIV 16 and DIV 32
Divide-by-32 counter can be acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
Flip-Flop and DIV 32
DIV 16 and DIV 32
Question # 2 of 10 ( Start
time: 03:05:20 PM ) Total Marks: 1
The counter states or the range of numbers of a counter is determined by the formula. (“n” represents the total number of flip-flops)
Select correct option:
(n raise to power 2)
(n raise to power 2 and then minus 1)
(2 raise to power n)
(2 raise to power n and then minus 1)
The counter states or the range of numbers of a counter is determined by the formula. (“n” represents the total number of flip-flops)
Select correct option:
(n raise to power 2)
(n raise to power 2 and then minus 1)
(2 raise to power n)
(2 raise to power n and then minus 1)
Question # 3 of 10 ( Start
time: 03:06:36 PM ) Total Marks: 1
A 4- bit UP/DOWN counter is in DOWN mode and in the 1010 state. on the next clock pulse, to what state does the counter go?
Select correct option:
1001
1011
0011
1100
A 4- bit UP/DOWN counter is in DOWN mode and in the 1010 state. on the next clock pulse, to what state does the counter go?
Select correct option:
1001
1011
0011
1100
Question # 4 of 10 ( Start
time: 03:07:37 PM ) Total Marks: 1
A 4-bit binary UP/DOWN counter is in the binary state zero. the next state in the DOWN mode is___________
Select correct option:
0001
1111
1000
1110
A 4-bit binary UP/DOWN counter is in the binary state zero. the next state in the DOWN mode is___________
Select correct option:
0001
1111
1000
1110
Question # 5 of 10 ( Start
time: 03:09:04 PM ) Total Marks: 1
Divide-by-160 counter is acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Divide-by-160 counter is acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Question # 6 of 10 ( Start
time: 03:10:01 PM ) Total Marks: 1
A counter is implemented using three (3) flip-flops, possibly it will have ______ maximum output status.
Select correct option:
3
7
8
15
A counter is implemented using three (3) flip-flops, possibly it will have ______ maximum output status.
Select correct option:
3
7
8
15
Question # 7 of 10 ( Start
time: 03:10:49 PM ) Total Marks: 1
RCO stands for ________
Select correct option:
Reconfiguration Counter Output
Ripple Counter Output
Reconfiguration Clock Output
Ripple Clock Output
RCO stands for ________
Select correct option:
Reconfiguration Counter Output
Ripple Counter Output
Reconfiguration Clock Output
Ripple Clock Output
Question # 8 of 10 ( Start
time: 03:11:38 PM ) Total Marks: 1
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
Select correct option:
Race condition
Clock Skew
Ripple Effect
None of given options
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
Select correct option:
Race condition
Clock Skew
Ripple Effect
None of given options
Question # 9 of 10 ( Start
time: 03:12:20 PM ) Total Marks: 1
For a down counter that counts from (111 to 000), if current state is "101" the next state will be _______
Select correct option:
111
110
010
none of given options
For a down counter that counts from (111 to 000), if current state is "101" the next state will be _______
Select correct option:
111
110
010
none of given options
Question # 10 of 10 (
Start time: 03:13:03 PM ) Total Marks: 1
A Divide-by-20 counter can be acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
Flip-Flop and DIV 32
Div 10 and DIV 16
A Divide-by-20 counter can be acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
Flip-Flop and DIV 32
Div 10 and DIV 16
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