CS302 Quiz No. 3 File 3

In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is __________

0000

1111

0001

10000

If S=1 and R=0, then for positive edge triggered flip-flop Q(t+1) = _______

0

1

invalid

Input is invalid

In Master-Slave flip-flop setup, the master flip flop operates at ________

Positive half cycle of pulse

Negative half cycle of pulse

Both Master-Slave operate simultaneously

Master-Slave flip-flop does not operate on pulses, rather it is edge triggered.

If the S and R inputs of the gated S-R latch are connected together using a ____ gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)

AND

OR

NOT

XOR

The minimum time required for the input logic levels to remain stable before the clock transition occurs is known as the _________

Set-up time

Hold time

Pulse Interval time

Pulse Stability time (PST)

The 74HC163 is a 4-bit Synchronous Counter.it has..............parallel data inputs pins

2

4

6

8

We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), to supply the required frequency to each part of circuit, we can get help by using _________

Using S-R Flop-Flop

D-flipflop

J-K flip-flop

T-Flip-Flop

When the control line in tri-state buffer is high, the buffer operates like a ______ gate

XOR

AND

OR

NOT

A Divide-by-20 counter can be acheived by using

Flip-Flop and DIV 10

Flip-Flop and DIV 16

Flip-Flop and DIV 32

Div 10 and DIV 16

The ABEL symbol for “OR” operation is

&

#

$

!