CS302 Digital Logic and Design GDB No. 1, Fall 2013, Due Date: February 12, 2014

CS302 - GDB | Digital Logic and Design

Opening Date: Tuesday, February 11, 2014
Closing Date: Wednesday, February 12, 2014

TOPIC:
“An electric power supply company is going to make a power line network to monitor the power supply and line losses. For monitoring system to be deployed with this network, which integrated technology will be a better choice, as CMOS and TTL are widely used in different scenarios? Support you views with reasons. You may also point out a technology (if any) other than CMOS and TTL but with reasons.”

A concise, coherent and to the point comment is preferred over lengthy comment having irrelevant details. Your comment must not be more than 5-7 lines. Comments, posted on regular Lesson's MDB or sent through email will not be considered in any case. Any request about such an acceptance will not be catered.

Best of Luck!
[ Instructor CS302 ]

(An Idea Solution)

CMOS compared to TTL:
1. CMOS components are typically more expensive than TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation.
2. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power supply distribution, therefore causing a simpler and cheaper design.
3. Due to longer rise and fall times, the transmission of digital signals becomes simpler and less expensive with CMOS chips.
4. CMOS components are more susceptible to damage from electrostatic discharge than TTL


Characteristics of TTL logic:
1. Power dissipation is usually 10 mW per gate.
2. Propagation delays are 10 nS when driving a 15 pF/400 ohm load.
3. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1.


Characteristics of CMOS logic:
1. Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate.
2. Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 nS to 50 nS.
3. Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they are 20 - 40% longer than the propagation delays.
4. Noise immunity approaches 50% or 45% of the full logic swing.
5. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high.