Question # 1 of 10 ( Start time: 01:15:08 PM ) Total
Marks: 1
Asynchronous mean that_____________
Select correct option:
Each flip-flop after the first one is enabled by the output of the preceding flip-flop
Each flip-flop is enabled by the output of the preceding flip-flop
Each flip-flop except the last one is enabled by the output of the preceding flip-flop
Each alternative flip-flop after the first one is enabled by
Question # 2 of 10 ( Start time: 01:16:36 PM ) Total Marks: 1
A divide-by-10 ring counter requires a minimum of
Select correct option:
ten flip-flops
five flip-flops
four flip-flops
twelve flip-flops
Question # 3 of 10 ( Start time: 01:17:00 PM ) Total Marks: 1
When the number of states are reduced during the design any counter
Select correct option:
output changes and Input remain unchanged
Input changes and output remain unchanged
Input and output bith change
Input and output remain unchanged
Question # 4 of 10 ( Start time: 01:18:13 PM ) Total Marks: 1
In moore machine the output depends on
Select correct option:
the current state and the output of previous flip flop
only inputs
the current state
the current state and inputs
Question # 5 of 10 ( Start time: 01:18:37 PM ) Total Marks: 1
When an eight bit serial in/serial out shift register is used for a 24 micro seconds time delay, the clock frequenct must be
Select correct option:
41.67 KHz
333 KHz
125 KHz
8 MHz
Question # 6 of 10 ( Start time: 01:18:55 PM ) Total Marks: 1
To parallel load a byte of data into a shift register, there must be
Select correct option:
one clock pulse
one clock pulse for each 1 in the data
eight clock pulse
one clock pulse for each 0 in the data
Question # 7 of 10 ( Start time: 01:20:03 PM ) Total Marks: 1
Divide-by-160 counter is acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Question # 8 of 10 ( Start time: 01:20:39 PM ) Total Marks: 1
With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in
Select correct option:
80 micro seconds
8 micro seconds
80 mili seconds
10 micro seconds
Question # 9 of 10 ( Start time: 01:20:54 PM ) Total Marks: 1
Once the state diagram is drawn for any sequential circuit the next step is to draw
Select correct option:
Transiation table
Karnaugh map
Next-state table
Logic expression
Question # 10 of 10 ( Start time: 01:21:17 PM ) Total Marks: 1
A modulus-14 counter has fourteen states requiring_____________
Select correct option:
14 Flip Flops
14 Registers
4 Flip Flops
4 Registers
Asynchronous mean that_____________
Select correct option:
Each flip-flop after the first one is enabled by the output of the preceding flip-flop
Each flip-flop is enabled by the output of the preceding flip-flop
Each flip-flop except the last one is enabled by the output of the preceding flip-flop
Each alternative flip-flop after the first one is enabled by
Question # 2 of 10 ( Start time: 01:16:36 PM ) Total Marks: 1
A divide-by-10 ring counter requires a minimum of
Select correct option:
ten flip-flops
five flip-flops
four flip-flops
twelve flip-flops
Question # 3 of 10 ( Start time: 01:17:00 PM ) Total Marks: 1
When the number of states are reduced during the design any counter
Select correct option:
output changes and Input remain unchanged
Input changes and output remain unchanged
Input and output bith change
Input and output remain unchanged
Question # 4 of 10 ( Start time: 01:18:13 PM ) Total Marks: 1
In moore machine the output depends on
Select correct option:
the current state and the output of previous flip flop
only inputs
the current state
the current state and inputs
Question # 5 of 10 ( Start time: 01:18:37 PM ) Total Marks: 1
When an eight bit serial in/serial out shift register is used for a 24 micro seconds time delay, the clock frequenct must be
Select correct option:
41.67 KHz
333 KHz
125 KHz
8 MHz
Question # 6 of 10 ( Start time: 01:18:55 PM ) Total Marks: 1
To parallel load a byte of data into a shift register, there must be
Select correct option:
one clock pulse
one clock pulse for each 1 in the data
eight clock pulse
one clock pulse for each 0 in the data
Question # 7 of 10 ( Start time: 01:20:03 PM ) Total Marks: 1
Divide-by-160 counter is acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Question # 8 of 10 ( Start time: 01:20:39 PM ) Total Marks: 1
With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in
Select correct option:
80 micro seconds
8 micro seconds
80 mili seconds
10 micro seconds
Question # 9 of 10 ( Start time: 01:20:54 PM ) Total Marks: 1
Once the state diagram is drawn for any sequential circuit the next step is to draw
Select correct option:
Transiation table
Karnaugh map
Next-state table
Logic expression
Question # 10 of 10 ( Start time: 01:21:17 PM ) Total Marks: 1
A modulus-14 counter has fourteen states requiring_____________
Select correct option:
14 Flip Flops
14 Registers
4 Flip Flops
4 Registers
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