CS302 Current Final Term Paper Fall 2013 File 11

Total Questions: 52
40 MCQ’S : 40 Marks                        4 Questions: 2 Marks
4 Questions: 3 Marks                          4 Questions: 5 Marks
(5-7)MCQ’s are from Moaz objective file
 Some MCQ’S are:

• The simplest and most commonly used decoders are the ________

n to 2ⁿ         (n-1) to 2ⁿ              n to 2^n-1                 (n-1) to (2^n-1)

• OLMC consists of a _______

Encoder                decoder                 logic gate               flip-flop

• A Quad 1-to-4 MUX has ________ multiplexer.

2                 3                 4                 1

• The 4bit 2’s complement representation of “+5” is ________

1010                      1110                      1011                      0101

• The binary representation of 20 is __________

01100          10100                    00101                    11100

• A latch has ______ stable states.

1                 2                 3                 4

• Invalid state of NOR based SR latch occurs when ________

S=0,R=0               S=0,R=1               S=1,R=0               S=1,R=1

• _________ is used to simplify the circuit that determines the next state.

State diagram         next state table                state reduction                 state assignment

• A particular full adder has _______inputs and _______ outputs.

2,3               2,2               3,2               3,3

• A counted implemented using three flip flops will have maximum _____ output.

3                 7                 8                 15

• The high density FLASH memory cell is implemented using_____

1-floating gate MOS        2-floating gate MOS        4-floating gate MOS
6-floating gate MOS

• In a binary weighted D/A converter, the resistors on the inputs are:

Limit the power consumption              Prevent loading on the source
Determine the weights of the digital inputs
Determine the amplitude of the digital inputs
                
Subjective:

2 MARKS:

Write down 4 uses of multiplexer.

What is meant by state assignment process?

The groups of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. What will be the contents of register after 2 clock pulses?

What is the function of quantization process?

3 MARKS:

Convert the following expression in SOP form:

1. AB+B(CD+EF)

1. (A+B)+C

Write 3 points of difference between DRAM and SRAM.

Given the following statement used in PLD programming: Y PIN 23 ISTYPE „com‟; Explain what this statement means? Answer:- (Page 360) The statement describes Y available at output pins 23. The Y variable is a ‘Combinational’ output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement.

Draw circuit diagram of operational amplifier used as an inverting amplifier.

5MARKS:

Analyze and explain what is happening in this diagram?


Draw the state diagram of a 3-bit-up-down counter. Use an external input X, when X sets to logic 1, the counter counts downwards otherwise counts upward.

Analog to digital converters exhibit different types of errors during their conversion operation. Explain at least two.

Given below is an incomplete circuit diagram of parallel in / serial out shift register, in which Q0, Q1, Q2, Q3, and Clock input are disconnected. Connect above mentioned connections in such a way that functionality of the given circuit is not affected.