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CS302 Quiz No.3 Shared by Arhaam Abbas

Question # 1 of 10 ( Start time: 07:34:41 PM )  Total Marks: 1
If S=1 and R=1, for negative edge triggered flip-flop then Q(t+1) = _________
Select correct option:
 0
 1
 Invalid  ok
 Input is invalid


Question # 2 of 10 ( Start time: 07:35:41 PM )  Total Marks: 1
A decade counter is __________
Select correct option:
 Mod-3 counter
 Mod-5 counter
 Mod-8 counter
 Mod-10 counter  ok


Question # 3 of 10 ( Start time: 07:36:01 PM )  Total Marks: 1
An Astable multivibrator is known as a(n) _______
Select correct option:
 Oscillator  ok
 Booster
 One-shot
 Dual-shot


Question # 4 of 10 ( Start time: 07:36:27 PM )  Total Marks: 1
A synchronous decade counter will have _______ flip-flops
Select correct option:
 3
 4  ok
 7
 10


Question # 5 of 10 ( Start time: 07:36:55 PM )  Total Marks: 1
The glitches due to "Race Condition" can be avoided by using a ___________
Select correct option:
 Gated flip-flops
 Pulse triggered flip-flops
 Positive-Edge triggered flip-flops
 Negative-Edge triggered flip-flops  ok


Question # 6 of 10 ( Start time: 07:37:31 PM )  Total Marks: 1
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
Select correct option:
 Doesn’t have an invalid state  ok
 Sets to clear when both J = 0 and K = 0
 It does not show transition on change in pulse
 It does not accept asynchronous inputs


Question # 7 of 10 ( Start time: 07:37:58 PM )  Total Marks: 1
Divide-by-32 counter can be acheived by using
Select correct option:
 Flip-Flop and DIV 10
 Flip-Flop and DIV 16
 Flip-Flop and DIV 32
 DIV 16 and DIV 32


Question # 8 of 10 ( Start time: 07:39:13 PM )  Total Marks: 1
A 4- bit UP/DOWN counter is in DOWN mode and in the 1010 state. on the next clock pulse, to what state does the counter go?
Select correct option:
 1001
 1011
 0011
 1100


Question # 9 of 10 ( Start time: 07:39:56 PM )  Total Marks: 1
____________ is said to occur when multiple internal variables change due to change in one input variable
Select correct option:
 Hold and Wait
 Clock Skew
 Race condition  ok
 Hold delay


Question # 10 of 10 ( Start time: 07:40:32 PM )  Total Marks: 1
In Master-Slave flip-flop setup, the master flip flop operates at __________
Select correct option:
 Positive half cycle of pulse
 Negative half cycle of pulse
 Both Master-Slave operate simultaneously
 Master-Slave flip-flop does not operate on pulses, rather it is edge triggered.

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In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is __________ 0000 1111 0001 10000 If S=1 and R=0, then for positive edge triggered flip-flop Q(t+1) = _______ 0 1 invalid Input is invalid In Master-Slave flip-flop setup, the master flip flop operates at ________ Positive half cycle of pulse Negative half cycle of pulse Both Master-Slave operate simultaneously Master-Slave flip-flop does not operate on pulses, rather it is edge triggered. If the S and R inputs of the gated S-R latch are connected together using a ____ gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) AND OR NOT XOR The minimum time required for the input logic levels to remain stable before the clock transition occurs is known as the _________ Set-up time Hold time Pulse Interval time Pulse Stability time (PST) The 74HC163 is a 4-bit Synchron...