In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is __________ 0000 1111 0001 10000 If S=1 and R=0, then for positive edge triggered flip-flop Q(t+1) = _______ 0 1 invalid Input is invalid In Master-Slave flip-flop setup, the master flip flop operates at ________ Positive half cycle of pulse Negative half cycle of pulse Both Master-Slave operate simultaneously Master-Slave flip-flop does not operate on pulses, rather it is edge triggered. If the S and R inputs of the gated S-R latch are connected together using a ____ gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) AND OR NOT XOR The minimum time required for the input logic levels to remain stable before the clock transition occurs is known as the _________ Set-up time Hold time Pulse Interval time Pulse Stability time (PST) The 74HC163 is a 4-bit Synchron...
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